Senior Staff Engineer Design

Join our world-class silicon design team and play a key role in developing next-generation semiconductor products. We are looking for an experienced RTL Design Engineer who can drive the complete design cycle from specification to micro-architecture, RTL implementation, and quality sign-off while optimizing for Power, Performance, and Area (PPA). This is an opportunity to work closely with architecture, verification, and implementation teams on cutting-edge SoC/IP development.

Your role
Key responsibilities in your new role

• Own the RTL design cycle from specification analysis to micro-architecture definition and RTL implementation.

• Develop detailed micro-architecture documents from high-level product specifications.
• Translate architecture and design requirements into high-quality RTL using Verilog/SystemVerilog.
• Collaborate with architecture teams to review and refine design and micro-architecture proposals.
• Deliver RTL that is functionally correct and optimized for Power, Performance, and Area (PPA).
• Drive RTL quality sign-off activities including Lint, CDC, Synthesis, and CLP checks.
• Implement and review low-power design methodologies using UPF and related power-intent constructs.
• Work closely with verification, physical design, and integration teams to resolve design issues.
• Debug and root-cause functional, synthesis, timing, and low-power challenges.
• Ensure compliance with coding standards and design best practices throughout the development cycle.
• Support design reviews and provide technical mentorship to junior engineers when required.

Your profile
Qualifications and skills to help you succeed 

• Experience: 8+ years of RTL Design experience in the semiconductor industry.

• Education: B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, or related disciplines.
• Strong experience in converting specifications into micro-architecture and RTL implementation.
• Expert-level proficiency in Verilog and System Verilog.
• Hands-on experience with Lint, CDC, Synthesis, and CLP sign-off methodologies.
• Strong understanding of low-power design techniques and UPF constructs.
• Good knowledge of AMBA protocols, including AHB and AXI.
• Experience designing complex digital blocks with a focus on PPA optimization.
• Strong debugging and problem-solving skills across the RTL development lifecycle.
• Excellent collaboration and communication skills with cross-functional engineering teams.

#WeAreIn for driving decarbonization and digitalization.
As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
Are you in?

We are on a journey to create the best Infineon for everyone.

We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. 

Our hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.

Please let your recruiter know if you need any accommodations during the interview process.

Learn more about our various contact channels and about Diversity & Inclusion at Infineon.

Keerthini M H