Clera

Senior Silicon Engineer

San Francisco, California · On-site · Posted today

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Salary
Not listed
Job type
Full-time
Work mode
On-site
Source
Ashby (employer's hiring system)

Skills mentioned

FPGA, RTL, Python, Firmware, Verilog, SystemVerilog, ASIC

About the role

About the Role

As a founding silicon team member at a well-funded AI accelerator startup, you will lead the full journey of a custom XPU from FPGA prototype through tapeout and bring-up. This is a high-ownership, high-impact role that sets technical direction across architecture, RTL, verification, and tooling while the silicon organization grows around you.

What You'll Do

  • Lead FPGA prototype development and optimization of the XPU, taking designs from specification to working silicon.

  • Design and review RTL destined for the first ASIC, ensuring clean microarchitecture and synthesizable code.

  • Build lint, simulation, synthesis, timing, and verification flows to support rapid iteration and tapeout readiness.

  • Make architecture decisions spanning compute datapaths, memory systems, on-chip interconnect, and control logic.

  • Drive the design through tapeout, bring-up, and delivery milestones, including critical-sprint periods.

  • Grow and mentor the silicon team as the company scales.

What We're Looking For

  • 8 or more years of hands-on digital design or silicon engineering experience building RTL, FPGA prototypes, or ASICs.

  • Proven ability to ship synthesizable SystemVerilog or Verilog in production silicon or FPGA designs.

  • End-to-end FPGA experience: RTL through synthesis, place-and-route, and deployment to working hardware.

  • Strong fundamentals in pipelining, clocks, resets, latency, throughput, and microarchitecture.

  • Fluency with simulation, linting, synthesis, SDC constraints, timing closure, and CDC verification flows.

  • Experience automating hardware flows using Python, Tcl, Make, Nix, or similar tools.

  • Background designing or optimizing AI accelerators or low-level AI kernel implementations.

  • Tapeout experience, high-speed interface design, formal verification, UVM, cocotb, firmware, or systems programming are strong advantages.

  • Self-directed, comfortable with ownership, and energized by fast-moving environments.

Compensation & Benefits

Base salary range: $200,000 to $300,000 USD annually, plus equity. Visa sponsorship is available.

Location

Full-time, on-site in San Francisco, CA. This role is not remote or hybrid.

Job ID ab-clera-65775d78-6477-412c-8686-6525886419f7 · Original posting ↗